1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a structure of a ferroelectric capacitor for storage of information and a circuit of ferroelectric memory cells each using the above ferroelectric capacitor and is used in a ferroelectric memory, for example.
2. Description of the Related Art
Semiconductor memories are utilized in the main memories of large-scale computers, personal computers, domestic electric appliances, portable telephones or the like. Various types of semiconductor memories such as volatile DRAMs (Dynamic RAMs), SRAM (Static RAMs), nonvolatile MROMs (Mask ROMs), Flash EEPROMs and the like are put on the market. Particularly, even though the DRAM is a volatile memory, it is excellent in the low cost (the cell area is ¼ times that of the SRAM) and the high-speed operation (Flash EEPROM) and, at present, it substantially dominantly occupies the market. The rewritable and nonvolatile flash memory is of a nonvolatile type and data stored therein can be maintained even if the power supply thereof is turned OFF. However, since the EEPROM has disadvantages that the number of rewriting (W/E) operation times is only approximately 106, the write time of approximately several microseconds is required and high voltage (12V to 22V) is required for writing, it is not put on the market as widely as the DRAM.
On the other hand, nonvolatile ferroelectric memories each using a ferroelectric capacitor are of a nonvolatile type and have advantages that the number of rewriting (W/E) operation times is approximately 1012, the read/write (R/W) time is approximately the same as that of the DRAM and the 3V operation can be performed. Therefore, they can be dominantly used in the entire market and various makers study and develop the nonvolatile ferroelectric memories.
FIGS. 16A and 16B respectively show the structure of the conventional ferroelectric capacitor and an equivalent circuit of a ferroelectric memory using the ferroelectric capacitor.
The ferroelectric capacitor shown in FIG. 16A includes two electrodes 1, 2 and a ferroelectric film of perovskite structure of PbZrxTi(1−x)O3, for example, which is disposed between the electrodes and in which the relation between the electric field and remanent magnetic field has a hysteresis characteristic. With the above structure, voltage is applied between the two electrodes 1, 2 to generate an electric field and change the direction of polarization and thus one-bit information can be stored.
The ferroelectric memory cell shown in FIG. 16B includes a selection transistor Q and the ferroelectric capacitor C described before which are connected in series between a data line (bit line BL) and a plate line PL.
Therefore, data can be read or written with respect to the ferroelectric capacitor C via the bit line BL by setting the selection transistor Q into the ON state by use of drive voltage of a word line WL shown in FIG. 16B and causing inversion of polarization by use of drive voltage of the plate line PL.
FIGS. 16C and 16D show the crystal structure of the ferroelectric film of the ferroelectric capacitor shown in FIG. 16A and the polarization position in which information is stored.
In order to form the ferroelectric film, generally, a material having an ABO3 or ABxC(1−x)O3 perovskite structure such as PZT (PbZrxTi (1−x)O3) is used. For example, PbZrxTi(1−x)O3 has a perovskite structure in which a Ti-atom or Zr-atom whose atom position is moved by application of an electric field is arranged in the structure surrounded by O-atoms and Pb-atoms.
If voltage is applied between the electrodes lying at both ends to generate an electric field in a downward direction as shown in FIG. 16C, the tetravalent Ti-atom is moved or shifted in the downward direction from the center and stabilized in a position below the center after the electric field is returned to “0”. This is because a low potential portion exists in a portion below the center.
If voltage is applied between the electrodes lying at both ends to generate an electric field in an upward direction as shown in FIG. 16D, the tetravalent Ti-atom is moved in the upward direction from the center and stabilized in a position above the center after the electric field is returned to “0”. This is because a low potential portion also exists in a portion above the center.
However, in the conventional ferroelectric memory cell as described above, only two values (“1” and “0”), that is, only one-bit information can be stored in one ferroelectric capacitor and the development in high integration has limitations.
The inventor of this application proposed the configuration which attained the high integration density of ferroelectric memory cells according to “Semiconductor Memory Device and System having the same mounted thereon” of Jpn. Pat. Appln. KOKAI Publication No. 10-255483, “Semiconductor Memory Device” of Jpn. Pat. Appln. KOKAI Publication No. 11-177036, “Semiconductor Memory Device” of Japanese Patent Application No. 2000-22010 and the like. The above proposals relate to a system of a ferroelectric memory cell unit configured by connecting a ferroelectric capacitor and selection transistor in parallel and connecting a plurality of parallel-connected circuits in series. However, only two-value information can be stored in one ferroelectric capacitor.
As described above, the ferroelectric memory using the conventional ferroelectric memory cells can store only two-value information in one ferroelectric film and has a limitation in an increase in the integration density.